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Meteor Lake: Intel’s biggest architecture shift in 40 years to deliver significant gains

Tiles, Foveros Packaging, Power Optimised Architecture

Note: This feature was first published on 19 September 2023.

(Image source: Intel)

Meteor Lake is how Intel demonstrates that it’s firing on all its cylinders

Intel is throwing in everything but the kitchen sink with its upcoming Meteor Lake processor. The first everyday processor with an integrated NPU for AI at scale, more accelerators than any other CPU before it, double the graphics capabilities, a significant boost in performance per watt through its first-ever tile-based disaggregated architecture, the first processor to use the Intel 4 process node and the first volume consumer processor to use Foveros advanced packaging technology. We thought Alder Lake’s P-core and E-core implementation with the Intel Thread Director was huge, but frankly speaking, Meteor Lake’s advancements are off the charts.

In our books, it is a far superior processor than anything else released by Intel for consumers in recent years, technically speaking. Does that mean you’re going to get a 2x performance uplift? Perhaps in tasks involving the GPU, NPU or if you’re looking at power efficiency per watt. So yes, it won’t magically improve performance across the board for all tasks. Still, the idea of Meteor Lake is to debut notable advances to move the performance per watt efficiency in a big way and a testbed of all the new developments put together, including the new architecture type, new packaging, and more.

At Intel Innovation 2023, the company announced Meteor Lake would launch in the form of the upcoming Ultra Core processor lineup on 14th December. Meanwhile, let's dive in and get cosy with what Meteor Lake architecture has to offer.

Embracing chiplets(Tile-based) architecture in a new way

(Source: Intel)

Processors utilising multiple chips have been around for a long time now, but they usually involve either connecting multiple monolithic CPU dies on one package or a CPU talking to the platform chipset and on-package high-speed memory in one package.

However, the way Meteor Lake embraces Tiles is a brand new way, thanks to Foveros' die-stacking technology advanced packaging (which we’ve discussed in great detail in our Intel Malaysia chip assembly and packaging tour). Foveros allows Intel to marry different processor blocks, each manufactured on an ideal silicon process technology that’s best suited for the cost/performance optimisation fit for the target market of the processors. This improves efficiency in churning out various processor SKUs quickly, meaning greater customisation and time to market.

(Source: Intel)

And thanks to the high bandwidth, low latency links Foveros allows between the silicon base interposer and the tiles it connects with above, Intel doesn’t have to design complex monolithic core processor dies any longer. In fact, the brand-new Meteor Lake takes advantage of these benefits in a big way by deploying the following tiles that make up the processor:-

Compute Tile comprising of new P-core and E-cores (manufactured on the new Intel 4 process node)SoC Tile (manufactured on TSMC’s N6 process node)Graphics Tile (manufactured on TSMC’s N5 process node)I/O Tile (manufactured on TSMC’s N6 process node)

Architected for power optimisation

The debut of a new Low Power (LP) E-core in addition to the existing E and P-cores, as well as parking the new LP E-core within a power-optimized, all-in-one SoC tile, is a big move as part of the overall re-thinking of how Meteor Lake should be optimised for power efficiency for performance-per-watt output. (Image source: Intel)

The new disaggregated architecture not only allowed Intel to optimise the right dies to come together, but it also allowed them to redesign the blocks and interdependencies to embrace a modular and scalable power management architecture over an optimised and scalable fabric to deliver improved bandwidth and efficiency.

A typical processor block diagram prior to Meteor Lake. (Source: Intel)

One of the primary considerations was the repartitioning of compute-intensive processes for power optimisation. Intel studied that in their existing processors, the media processing block was inside the graphics complex attached next to the compute complex. This meant that with any video decode, encode or transcode request, many high-performance blocks and interconnects are awakened and thus consume too much power for a simple task that occurs pretty often in current everyday use case scenarios.

The new processor schema with Meteor Lake. (Image source: Intel)

To overcome the power inefficiencies of the past, Intel moved around and rearchitected several traditional blocks:-

Introduced a new SoC core (or tile) to incorporate several standard blocks essential for a system's operation without involving the heavy compute blocks. It is optimised for power efficiency.At its heart is a new dual-core Low Power (LP) E-core is at the heart of the SoC to handle any tasks that come its way; when it determines the process requires more horsepower, it hands the request over to the dedicated Compute tile. This is an evolution of the Hybrid Architecture that first debuted with Alder Lake and adds another stage: LP E-core è E-core è P-core. This is also marketed as the 3D Hybrid Architecture.It boasts a media engine carved out of the graphics core to manage all video workloads in the low-power SoC tile.Next, the display engine was plucked from the CPU die and is housed within the SoC tile.The memory controller, too, has been shifted from the CPU die and incorporated into the SoC tile to directly access system memory, which is swell when all other processor parts are in deep sleep. Still, it also has independent paths to all other processor tiles for them to tap on when suitable workloads and data transfer requests arrive.The main graphics engine is delegated to its own tile that’s optimised for 3D performance; all the heavyweight P and E cores are bunched together in a Compute tile optimised for CPU performance, and high-speed I/O like USB4, Thunderbolt 4, and PCIe Gen 5 are in their own I/O tile to improve I/O bandwidth scaling.

The SoC Tile. (Source: Intel)

In essence, the SoC tile is now the backbone of the Meteor Lake processor. Since it has most of the necessary processing blocks within itself, it will summon other compute and power-intensive blocks where appropriate. Depending on tasks and workloads, low throughput workloads can be offloaded to the new low-power E-core to shut off the main compute complex island, which results in massive power savings. This level of control comes at a minor penalty as more localised power management controllers are embedded on all the tiles to support this new hierarchy and a scalable fabric to bind them all together.

Sample of processor utilisation when the LP E cores are able to handle the workload. (Source: Intel)

During the Meteor Lake tech day event, Intel demoed an engineering laptop using a Meteor Lake processor that had been running a video for several hours; through monitoring the task manager, only Low Power E-core was being used. This shows their implementation works and thus delivers a more power-efficient laptop.

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